1. Field of the Invention
The present invention relates to a computer system, and more particularly, to a computer system for dividing a display area into a plurality of tiles and displaying images by a basic unit of a tile.
2. Description of the Prior Art
Monitor is one of the most important human-computer interfaces of computer systems. Monitor can display important information, numerical data, and graphic images to users. More and more monitors have graphical user interfaces (GUI) to enable users to easily and intuitively operate the computer system. With the recent development of information technology, more and more information is graphically expressed. For instance, computer aided design (CAD) software, and video-communication with remote networks all demand better monitors. Therefore, monitors and related devices of computer systems are important topics of modern information technology research and development.
Please refer to FIG. 1, which is a functional block diagram of a prior art computer system 10. The computer system 10 comprises a CPU 12, a northbridge circuit 14A, a southbridge circuit 14B, peripheral devices 14C, a graphics card 16, and a monitor 20. The monitor 20 displays images in a main display area 22. The CPU 12 is to control the operations of the computer system 10. The northbridge circuit 14A is to control data flow between the CPU 12 and the graphics card 16, while the southbridge circuit 14B is to control data flow between the CPU 12 and peripheral devices 14C through the intermediate northbridge circuit 14A. The peripheral devices 14C can be input devices (keyboard, mouse, etc) and storage devices (CD-ROM, HDD, etc). After digital data is processed by the CPU 12, the processed digital data is then transferred to the graphics card 16 to graphically display on the monitor 20. The graphics card 16 comprises a processing unit 18A and a memory 18B. Of course, chipset developers have variations of this such as the processing unit 18A being integrated into the northbridge 14A, and the memory 18B incorporated with system memory in the computer system 10.
In the monitor 20, the main display area 22 comprises display units A disposed in a plurality of columns and rows arranged as a matrix, and a controller 24 to control these display units A. As is shown in FIG. 1, a plurality of display units arranged from left to right can be classified as a row. An uppermost row in FIG. 1 is marked as row Rp(0), and a second uppermost row is marked as row Rp(1), and so on. If the main display area 22 comprises M rows, then the lowest row of FIG. 1 can be marked as Rp(M−1). When the main display area 22 displays an image, each display unit A displays a part of the image according to corresponding pixel data. Composing all that display units A display can generate a complete image. To control the contents of the main display area 22, the memory 18B comprises a plurality of memory units D, and each of the memory units D corresponds to a display unit A and stores pixel data. When the computer system 10 is going to display an image on the main display area 22, it temporarily stores the data of the images into the memory 18B, and then the processing circuit 18A reads the data from each memory unit D of the memory 18B. Then the data is image-processed to obtain the corresponding pixel data. Finally, the obtained pixel data is written back to each memory unit D of the memory 18B. Then the plurality of pixel data composing the image is transmitted to the controller 24 through the processing circuit 18A sequentially. In the prior art monitor 20, when the controller 24 receives the sequential pixel data it controls each display unit A according to the pixel data to display the image on the main display area 22.
To further illustrate how the controller 24 works, please refer to FIG. 2A. FIG. 2A is a schematic diagram of a controlling sequence of the display units A in the prior art monitor 20. To clearly illustrate the sequence of the controller 24 controlling all the display units A, the bracketed number of each display unit A represents its own position in the sequence. As is shown in FIG. 2A, the controller 24 makes the display units A display the image according to the corresponding pixel data. For example, the first pixel data in the sequence controls the display unit A(0), and the second pixel data in the sequence controls the display unit A(1) until N display units of the row Rp(0) sequentially displays images. Then the controller 24 controls the next row according to the next N pixel data. This continues row by row, until finally the A((M−2)*N) display unit to the A((M−1)*N−1) display unit of the row Rp(M−2) and the A((M−1)*N) display unit to the A(M*N−1) display unit of the row Rp(M−1) to finish the controlling of M*N display units of the main display area 22. According to the manner of row-by-row and following the sequence of N display units A in each row, the controller 24 can control the corresponding display units A to display the sequential pixel data.
As is mentioned above, the processing circuit 18A of the graphics card 16 shares responsibility with the CPU 12 to generate pixel data before processing images besides sequentially transmitting pixel data to the controller 24. From the point view of image processing, the pixel data of adjacent display units in the main display area 22 have more relevance and can be regarded as one entity. In general cases, adjacent display units have similar colors and brightness. For example, in the field of computer graphics (CG), anti-aliasing gives intermediate colors and brightness to pixels in border regions of a portion of the image having too sharp a contrast. The pixel data of adjacent display units have more relevance during image processing. In order to efficiently execute image processing, grouping adjacent display units into a tile as a unit for image processing is adopted. Please refer to FIG. 2B. FIG. 2B is a schematic diagram of adjacent display units forming basic tiles for image processing. As is shown in FIG. 2A, in FIG. 2B each display unit A shows its position in sequence by a bracketed number. Assuming that a tile is formed by Mt rows and Nt columns of adjacent display units, the status of the main display area 22 after tiling is shown in FIG. 2B. The main display area 22 is divided into (M*N)/(Mt*Nt) tiles. A first tile can be marked as tile Tp(0), which consists of display units of a first Nt columns of rows Rp(0) to Rp (Mt−1). A second tile can be marked as tile Tp(1), which consists of display units of a second Nt columns of rows Rp(0) to Rp(Mt−1). The display units of the second tile Tp(1) includes display units A (Nt) to A(2Nt−1) in row Rp(0) and display units A((Mt−1)*N+Nt) to A ((Mt−1)*N+2Nt−1)) in row Rp(Mt−1). A last tile can be marked as tile Tp((M*N)/(Mt*Nt)−1), which consists of display units of a last Nt columns of rows Rp(M−Mt) to Rp(M−1). The display units of the tile Tp((M*N)/(Mt*Nt)−1) includes display units A((M−Mt+1)*N−Nt) to A((M−Mt+1)*N−1) in row Rp(M−Mt), and display units A(M*N−Nt) to A(M*N−1) in row Rp(M−1).
As is discussed formerly, the processing circuit 18A of the computer system 10 accesses the pixel data of the memory 18B for image processing, then transmits the pixel data one by one to the controller 24. The controller 24 can then make the display units A display the image in the same sequence shown in the FIG. 2A. Since the memory units D of the memory 18B are for storing corresponding pixel data of the display units A, an allocation type of each memory unit D affects the efficiency of the processing unit 18A when accessing the memory 18B. Please refer to FIG. 3A. FIG. 3A is a schematic diagram of the allocation type of each memory unit D when the memory 18B is under a linear address mode. To mark the display unit A corresponding to the memory unit D, each memory unit D in FIG. 3 has a number of its corresponding display unit A shown in brackets. In other words, the data stored in the memory unit D(m) is the pixel data of the display unit marked as A(m). As is shown in FIG. 3A, the linear address mode of the memory 18B is to store the N pixel data of the same row into adjacent memory units. For example, N display units A(0) to A(N−1) of the row Rp(0) have the corresponding N pixel data stored in the sequential N memory units D(0) to D(N−1) of the memory 18B, and similarly, the N display units of the row Rp(1) have the corresponding N pixel data stored in the following N sequential memory units D(N) to D(2N−1) of the memory 18B. Finally, the N display units of the row Rp(M−1) store their pixel data in the N sequential memory units starting from the memory unit D((M−1)*N) to D(M*N−1). When the processing circuit 18A of the graphics card 16 is transferring the pixel data to the controller 24 by the linear address mode in the FIG. 3, the controller 24 controls the display of images in the sequence of display units A(0), A(1) and so on. Then the processing unit 18A can directly and sequentially transmit data starting with the memory unit D(0) to the controller 24, in order to display the image on the main display area 22.
Though the linear address mode of the memory 18B in FIG. 3A can conveniently to directly transmit pixel data sequentially to the controller 24 of the monitor 20, however, when the processing circuit 18A is going to perform image processing, access efficiency of the memory 18B is deteriorated. Please refer to FIG. 3B, which is a schematic diagram of the memory 18B being accessed while the processing circuit 18A is performing image processing. As is illustrated and discussed with reference to FIG. 2B, dividing the display units A into tiles is better for the processing circuit 18A executing image processing. However, the linear address mode of FIG. 2B stores pixel data into memory units D under a linear address mode, if the processing unit 18A is going to access the related information of a tile, it must discontinuously access the memory units D because a tile is composed of a plurality of columns and rows. The operation of discontinuously accessing results in page misses, and each page miss causes penalties in latency. Therefore, though the linear address mode allows transmitting pixel data to the controller 24 by sequentially access, it results in a low processing efficiency because of the discontinuous accessing of a tile pixel data when executing image processing.
In contrast to the linear address modes of FIG. 3A and FIG. 3B, there is another type of memory allocation, called “tiled mode”. Please refer to FIG. 4A and FIG. 4B. FIG. 4A and FIG. 4B are schematic diagrams of pixel data being transmitted and image processing being performed in tiled mode, wherein each memory unit D is for storing the pixel data of the each display unit A. Under the tiled mode, all display units in the same tile have their corresponding pixel data stored sequentially into adjacent memory units. As is shown in FIG. 4A, Mt*Nt sets of pixel data corresponding to Mt*Nt display units (Mt rows, each row having Nt columns) of the tile Tp(0) are stored sequentially in the adjacent Mt*Nt memory units of the memory 18B. In the same way, Mt*Nt sets of pixel data of the tile Tp(1), comprising from the display units A(Nt) to A(2Nt−1) corresponding to the row Rp(0) to the display units A((Mt−1)*N+Nt) to A((Mt−1)*N+2Nt−1) corresponding to the row Rp(Mt−1), are stored sequentially into the adjacent Mt*Nt memory units of the memory 18B. Finally, Mt*Nt sets of pixel data of the tile Tp(M*N/(Mt*Nt)−1) are stored in the last continuous Mt*Nt memory units.
As is shown in the FIG. 4A, when executing image processing and in tiled mode, the processing circuit 18A can continuously access the pixel data instead of discontinuously crossing several memory pages to access all the pixel data of a tile. However, as is shown in FIG. 4B, when the processing circuit 18A is to transmit the pixel data sequentially to the controller 24 for displaying the image, the controller 24 makes the display units display the image in the sequence of the row numbers, which is illustrated in the FIG. 2A. Therefore, the processing circuit 18A must access the pixel data in the memory 18B and transmit them to the controller 24 in the same sequence. For example, when the processing circuit 18A transmits N pixel data of the row Rp(0) to the controller 24, it must read Nt sets of pixel data of the tile Tp(0) from the first Mt*Nt memory units, then cross to the following Mt*Nt memory units to read another Nt sets of pixel data of the row Rp(0) of the tile Tp(1). Similarly, the processing circuit 18A reads the last Nt sets of pixel data of the row Rp(0) from the Mt*Nt memory units of the tile Tp(N/Nt−1). The processing circuit 18A can collect the complete pixel data of the row Rp(0) by the above mentioned method, and then transmit them to the controller 24 for the display units of the row Rp(0) thereby displaying the image sequentially.
To sum up the above discussion it can be concluded that when under the linear address mode shown in FIG. 3A and FIG. 3B, the processing circuit 24 can sequentially read from the memory 18B and transmit the data sequentially to the controller 24. However, when the processing circuit 18A is processing the image, it must discontinuously access the pixel data instead of continuously accessing the pixel data when under the tiled mode, which is shown in FIG. 4A and FIG. 4B. The method has such a drawback that when the processing circuit 18A is transmitting pixel data to the controller 24, it must discontinuously access the memory units D of the memory 18B in the same sequence of the controller 24 controlling the display units A. This degrades access efficiency.
When under the linear address mode and the processing circuit 18A is accessing the corresponding pixel data, each time processing circuit 18A accesses 32*32 sets of pixel data of a tile, the processing circuit 18A needs to access pixel data scattered over 32 rows. Since a memory page has two rows of pixel data stored therein, collecting a tile of pixel data causes 16 page misses. As the main display area has 24*32 tiles, 12288 (16*24*32) page misses occur in order to access all the pixel data of the main display area 22. When the processing circuit 18A reads the data in the memory 18B and sequentially transmits the data to the controller 24, 384 (768/2) page misses will occur since a page has two rows of pixel data, and the main display area has 768 rows. The above-mentioned problem is illustrated in FIG. 3A.
When in the tiled mode and the processing circuit 18A is accessing the corresponding pixel data, since a page has two tiles of pixel data and the main display area has 24*32 tiles, then 384 (24*32/2) page misses occur, which is shown in FIG. 4A. As is shown in FIG. 4B, when the processing circuit 18A sequentially transmits the pixel data of each row to the controller 24, the processing circuit 18A crosses 32 tiles to completely collect a row of 1024 sets of pixel data. As each page has two tiles of pixel data, and the main display area has 768 rows, then 12288 (768*32/2) page misses occur.
The above-mentioned information shows that in the prior art monitor 20, the controller 24 can only accept pixel data transmitted sequentially to correctly control the outputted image of each display unit A. However, when processing an image, tiled allocation of memory is more efficient. Therefore, there is a trade-off between the linear address mode and the tiled mode.
Furthermore, the monitor 20 needs to refresh the screen at a specific refresh frequency, and each refreshing requires transmitting and processing of the pixel data of all display units A in the main display area 22. The more memory page misses that occur, the more is demanded from the graphics card 16. High demand to the graphics card 16 generates excessive heat and heat sinks are required on chips of the graphics card 16, which makes the design of the graphics card 16 more complicated and of higher cost.